An image sensor array has a plurality of active light-sensing pixels for receiving radiation from a target object arranged in columns and rows. One such CMOS image sensor is described in U.S. Pat. No. 5,471,515.
A column parallel architecture may read out an entire column of these image sensors at a readout time. For example, a sensor row decoder may operate to address rows of pixels.
A column buffer array has multiple buffer cells with each corresponding to a column of the image sensor array. Each column buffer cell receives signals from an addressed active pixel of the pixel array 110 to generate a signal. That signal is induced only based on the received radiation in that pixel.
Each column of the pixel array may have a dedicated readout signal chain and its own analog to digital (A/D) converter. The A/D converter is physically located at an area adjacent to the pixel array to convert the pixels that are from that area. Each row of pixels is read simultaneously into the parallel signal chain. The entire row is then converted to a digital code, in parallel by that A/D converter.
As the pixel pitches become smaller, it becomes increasingly difficult to fit the A/D converter layout into the area that is occupied by the pitch of one pixel column. One possible way of addressing this is to dedicate an A/D converter to multiple columns so that the A/D converter pitch can be multiple columns wide. A possible drawback with this approach, however, is that the pixel voltage will need to be time multiplexed into the shared A/D converter during the row time, thus slowing the conversion.
In operation, the signals are sampled and held, and then driven into the A/D converter in parallel. A buffer amplifier holds and multiplexes the signals to the A/D converter. The buffer amplifier should support a wide output voltage swing in order to maintain the dynamic range of the sensor. Moreover, the buffer amplifier should not attenuate the signal or add noise, since this would also reduce the performance of the sensor. It is also important that the buffer amplifier has a fast response in order to drive multiple pixel voltages into the A/D converter during the row time thus allowing sufficient time for the A/D conversion operation.
A conventional design for the sample and hold buffer is illustrated in FIG. 1. The input voltages are shown as 100, 102 . . . 104 and can include any desired number of input voltages, represented by the designation M. Only two input voltage stages are shown in FIG. 1 for simplicity, however, more generally, there can be M of these stages. Each of these input voltages are driven into a capacitor. For example, the input voltage 100 is driven to a capacitor 110. The capacitor also includes connection 122 to a clamping voltage 123. The pixel outputs are connected in parallel to the capacitors, to cause the values in the pixels to be sampled onto the capacitors 110, 111. When the sample and hold switches 125 (SH1) and 126 (SH2) are opened in each of the legs, the voltages are then held on the sample and hold capacitors 110, 111. Hence, these capacitors 110 111 act as sample and hold capacitors.
The sample voltages are then read out and driven into the A/D converter stage 160 via the buffering stage 150, one by one. In order to read out the sampled voltages, the amplifier 150 is first reset to clear the charge on its feedback capacitor 151 by closing the reset switch 152. Then, a capacitor is selected. Capacitor 110 is selected using the select 1 switch (127 in leg 100) and the select 2 switch (122 in leg 100). This puts the clamping voltage on one side of the capacitor and hence transfers the charge to the amplifier stage 150. The amplifier acts to transfer the charge from the selected sample and hold capacitor here 110, to the feedback capacitor 151 in the buffer stage. This effectively copies the sampled voltage to the output, and drives it into the A/D converter stage 160.